1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of manufacturing the same. More particularly, the present invention relates to a semiconductor memory device having a charge trapping layer formed via self-alignment and a method of manufacturing the same.
A claim of priority is made to Korean Patent Application No. 2003-92502 filed on Dec. 17, 2003, the disclosure of which is incorporated herein by reference in its entirety.
2. Description of the Related Art
A nonvolatile memory device retains stored data even in the absence of a power supply. A Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) nonvolatile memory device with an Oxide-Nitride-Oxide (ONO) structure capable of trapping charges and having a single MOSFET gate electrode is disclosed, for example, in U.S. Pat. No. 5,768,192. The SONOS nonvolatile memory device is readily manufactured and integrated within a peripheral region and/or a logic region of an integrated circuit.
However, in the conventional SONOS nonvolatile memory device, the ONO layer is provided on the entire surface of a channel region. This configuration increases the overall thickness of an effective oxide layer of a gate oxide layer. For this reason, the SONOS nonvolatile memory device has a high initial threshold voltage, a correspondingly high electric power dissipation, and high programming current. Furthermore, electrons trapped by a silicon nitride layer are apt to move horizontally along the silicon nitride layer. As a result, the time required to erase data in the nonvolatile memory device (“erasure time”) increases. Also, an initial threshold voltage (Vth) associated with an erased cell is likely to increase after repeated programming and erasing operations. Accordingly, on-cell current and readout speed may degrade over time along with a general ability to retain data.
To solve these problems, a conventional local SONOS nonvolatile memory device has been suggested in which a charge trapping layer, i.e., a silicon nitride layer, partially overlaps a gate electrode. Hereinafter, the conventional local SONOS nonvolatile memory device will be described with reference to FIGS. 1 through 4.
Referring to FIG. 1, first silicon oxide layer 12, silicon nitride layer 14, and second silicon oxide layer 16 are sequentially stacked on an upper surface of silicon substrate 10. Then, to pattern second silicon oxide layer 16, silicon nitride layer 14 and first silicon oxide layer 12, first photoresist pattern 18 is formed via a typical photolithography process. An exposed portion of second silicon oxide layer 16, silicon nitride layer 14, and first silicon oxide layer 12 are etched using first photoresist pattern 18 as an etch mask.
As shown in FIG. 2, after removing first photoresist pattern 18, gate oxide layer 20 is deposited on an upper surface of the resultant structure. By doing so, a portion of silicon substrate 10 is covered by gate oxide layer 20 and the other portion thereof is covered by ONO layer 22.
Referring to FIG. 3, polysilicon layer 24 is deposited on an upper surface of gate oxide layer 20 and ONO layer 22. Second photoresist pattern 26 for defining a gate electrode is formed on an upper surface of polysilicon layer 24.
As shown in FIG. 4, polysilicon layer 24 and ONO layer 22 are patterned using second photoresist pattern 26 as an etch mask to define gate electrode 25. Thereafter, second photoresist pattern 26 is removed. Gate electrode 25 overlaps both gate oxide layer 20 and ONO layer 22. Then, impurities are implanted into silicon substrate 10 at both outward edges of gate electrode 25 to form source and drain regions 28a and 28b. When two memory cells are formed to compose gate electrode 25 as described above, it is referred to as a 2-bit formation.
ONO layer 22 partially overlaps gate electrode 25 to lower an initial threshold voltage and reduce erasure time.
However, the foregoing conventional local SONOS nonvolatile memory device experiences problems resulting from the inconsistent formation of ONO layer 22 using the foregoing photolithography process.
As described above, the length of ONO layer 22 is determined by first and second photoresist patterns 18 and 26. However, the second photoresist pattern 26 that defines gate electrode 25 may be misaligned as shown by the pattern offset 26a in FIG. 3, while performing the photolithography process. This offset results in a variation of the length of ONO layer 22. In more detail, once polysilicon layer 24 and ONO layer 22 are patterned by an offset second photoresist pattern 26a, misalignment of the lengths of ONO layer 22, i.e., lengths L1 and L2 overlapping gate electrode 25 as shown in FIG. 5, may be different from each other. Here, respective memory cells are designated as even and odd cells. Accordingly, the lengths of ONO layer 22 differ between the even and odd cells.
If the lengths of ONO layer 22 are different from each other, the memory devices connected to ONO layer 22 may have different threshold voltages and erasure speeds. Consequently, the uniformity of nonvolatile memory device performance is degraded and the threshold voltage varies greatly.
It will be understood that when an element such as layer, region or substrate is referred to as being “on” or “onto” another element, the element is either directly on the other element or intervening elements may also be present.